View KS57C2504_1786491.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KS57C2504 4-bit cmos microcontroller product specification 4? 1 overview the s3c7254 single-chip cmos microcontroller has been designed for high performance using samsung's newest 4 -bit cpu core, sam4 (samsung arrangeable microcontrollers). with a two-channel comparator, up-to- 320-dot lcd direct drive capability, 8-bit timer/counter, and serial i/o, the s3c7254 offers an excellent design solution for a wide variety of applications which require lcd func tions. up to 27 pins of the 80-pin qfp package can be dedicated to i/o. eight vectored interrupts provide fast response to internal and external events. in addi tion, the s3c7254 's advanced cmos technology pro vides for low power consumption and a wide oper at ing voltage range. features memory ? 512 4-bit ram ? 4096 8-bit rom 27 i/o pins ? i/o: 15 pins ? input only: 4 pins ? output only: 8 pins comparator ? two-channel mode: internal reference (4-bit resolution) ? one-channel mode: external reference lcd controller/driver ? 40 segments and 8 common terminals ? 3, 4 and 8 common selectable ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? serial i/o interface clock generator watch timer ? time interval generation: 0.5 s, 3.9 ms at 32768 hz ? four frequency outputs to buz pin ? clock source generation for lcd 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive only mode ? lsb-first or msb-first transmission selectable ? internal or external clock source interrupts ? three internal vectored interrupts ? four external vectored interrupts ? two quasi-interrupts bit sequential carrier ? supports 16-bit serial data transfer in arbitrary format memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) oscillation sources ? crystal, ceramic, or rc for main system clock ? crystal oscillator for subsystem clock ? main system clock frequency: 4.19 mhz (typical) ? subsystem clock frequency: 32.768 khz ? cpu clock divider circuit (by 4, 8, or 64)
product specification s3c7254 4? 2 instruction execution times ? 0.95, 1.91, 15.3 s at 4.19 mhz ? 122 s at 32.768 khz operating temperature ? ? 40 c to 85 c operating voltage range ? 2.7 v to 6.0 v package type ? 80-pin qfp arithmetic logic unit interrupt control block stack pointer program counter program status word lcd driver/ controller vlc1?vlc5 com0?com7 seg0?seg31 p5.0/seg32? p5.7/seg39 512 x 4-bit data memory 4-kb program memory basic timer flags instruction decoder clock reset x in xt in x out xt out internal interrupts i/o port 4 p4.0/clo p4.1/tcl0 p4.2/tclo0 p1.0 / int0 / cin0 p1.1 / int1 / cin1 p1.2 / int2 p1.3 / int4 watch timer 8-bit timer/ counter sio input port 1 p0.0 / sck / k0 p0.1 / so / k1 p0.2 / si / k2 p0.3 / buz / k3 i/o port 0 compara- tor i/o port 2 i/o port 3 p2.0?p2.3 p3.0 p3.1 p3.2 / lcdsy p3.3 / lcdck figure 1. s3c7254 simplified block diagram
s3c7254 product specification 4? 3 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 xt out xt in x in x out v dd test reset p4.2 / tclo0 p4.1 / tcl0 p4.0 / cl o 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 KS57C2504 (top view) seg30 seg31 p5.0 / seg32 p5.1 / seg33 p5.2 / seg34 p5.3 / seg35 p5.4 / seg36 p5.5 / seg37 p5.6 / seg38 p5.7 / seg39 vss com0 com1 com2 com3 com4 com5 com6 com7 v lc1 v lc2 v lc3 v lc4 v lc5 p0.0 / sck / k0 p0.1 / so / k1 p0.2 / si / k2 p0.3 / buz / k3 p1.0 / int0 / cin0 p1.1 / int1 / cin1 p1.2 / int2 p1.3 / int4 p2.0 p2.1 p2.2 p2.3 p3.0 p3.1 lcdsy / p3.2 lcdck / p3.3 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 figure 2 . s3c7254 80? pin qfp assignment diagram s3c7254 (top view)
product specification s3c7254 4? 4 table 1. s3c7254 pin descriptions pin name pin type description number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is pos sible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 25 26 27 28 k0/ sck k1/so k2/si k3/buz p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit or 4-bit read and test are possible. the 1-bit unit pull-up resistors are assigned to input pins by software. an interrupt is generated by digital input at p1.0, p1.1. 29 30 31 32 int0/cin0 int1/cin1 int2 int4 p2.0?p2.3 i/o same as port 0 except that 8-bit read/write and test is possible. 33?36 ? p3.0 p3.1 p3.2 p3.3 37 38 39 40 ? ? lcdsy lcdck p4.0 p4.1 p4.2 i/o same as port 0 except that port 4 is 3-bit i/o port. 41 42 43 clo tcl0 tclo0 p5.0?p5.7 o output port for 1-bit data 3?10 seg32? seg39 sck i/o serial i/o interface clock signal 25 p0.0/k0 so i/o serial data output 26 p0.1/k1 si i/o serial data input 27 p0.2/k2 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output for buzzer sound 28 p0.3/k3 k0?k3 i/o external interrupt. the triggering edge is selectable. 25?28 p0.0?p0.3 int0 int1 i external interrupts. the triggering edge for int0 and int1 is selectable. 29 30 p1.0/cin0 p1.1/cin1 int2 i quasi-interrupt with detection of rising or falling edges 31 p1.2 int4 i external interrupts with detection of rising and falling edges 32 p1.3
s3c7254 product specification 4? 5 table 1. s3c7254 pin descriptions (continued) pin name pin type description number share pin cin0 cin1 i 2-channel comparator input. cin0: comparator input or external reference input cin1: compara tor input only. 29 30 p1.0/int0 p1.1/int1 lcdsy i/o lcd synchronization clock output for display expan - sion 39 p3.2 lcdck i/o lcd clock output for display expansion 40 p3.3 clo i/o clock output 41 p4.0 tcl0 i/o external clock input for timer/counter 0 42 p4.1 tclo0 i/o timer/counter 0 clock output 43 p4.2 seg32?seg39 o lcd segment signal output 3?10 p5.0?p5.7 seg0?seg29 seg30?seg31 o lcd segment signal output 51?80 1?2 ? com0?com7 o lcd common signal output 12?19 ? v lc1 ?v lc5 ? lcd power supply. voltage dividing resistors are assignable by mask option. 20?24 ? x in, x out ? crystal, ceramic or rc oscillator pins for system clock. 48, 47 ? xt in, xt out ? crystal oscillator pins for subsystem clock. 49, 50 ? v dd ? main power supply 46 ? v ss ? ground 11 ? reset i chip r eset signal input 44 ? test i chip test signal input (must be connected to v ss ) 45 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode.
product specification s3c7254 4? 6 table 2. s3c7254 pin descriptions pin name pin type share pin circuit type reset value p0.0?p0.3 i/o sck /k0, so/k1, si/k2, buz/k3 6 input p1.0?p1.1 i int0/cin0, int1/cin1 10 comparator p1.2?p1.3 i int2, int4 3 input p2.0?p2.3 i/o ? 5 input p3.0?p3.1 i/o ? 5 input p3.2?p3.3 i/o lcdsy, lcdck 5 input p4.0, p4.2 i/o clo, tclo0 5 input p4.1 i/o tcl0 6 input p5.0?p5.7 o seg32?seg39 7 high com0?com7 o ? 8 high seg0?seg31 o ? 8 high v dd ? ? ? ? v ss ? ? ? ? reset i ? 2 ? vlc1?vlc5 ? ? ? ? x in , x out ? ? ? ? xt in , xt out ? ? ? ? test i ? ? ?
s3c7254 product specification 4? 7 p - channel in n - channel v dd figure 3 . pin circuit type 1 p - channel in v dd pull-up resistor schmitt trigger pull-up resistor enable figure 5 . pin circuit type 3 in v dd pull-up resistor schmitt trigger figure 4 . pin circuit type 2 p - channel data output disable out n - channel v dd figure 6 . pin circuit type 4
product specification s3c7254 4? 8 p - ch data output disable v dd i/o pne n - ch pull-up resistor resistor enable v dd circuit type 1 figure 7 . pin circuit type 5 circuit type 9 seg output disable circuit type 4 data i/o figure 9 . pin circuit type 7 p - ch data output disable v dd i/o pne n - ch pull-up resistor resistor enable v dd schmitt trigger figure 8 . pin circuit type 6 p-ch n-ch v lc2 v lc3 v dd out seg/com data v lc1 v lc4 v lc5 figure 1 0 . pin circuit type 8
s3c7254 product specification 4? 9 v lc2 v lc3 v dd seg/com data v lc1 v lc4 v lc5 p - channel out n - channel output disable figure 1 1 . pin circuit type 9 in schmitt trigger in pull-up resistor resistor enable vdd ref (p1.0 only) in + _ ref digital or analog selectable by software p?ch. comparator int0/1 (digital) (analog) figure 1 2 . pin circuit type 10
product specification s3c7254 4? 10 program memory (rom) rom maps for s3c7254 devices are mask programmable at the factory. in its standard configuration, the device's 4,096 8-bit program memory has three areas that are directly addressable by the program counter (pc): ? 16-byte area for vector addresses ? 96-byte instruction reference area ? 16-byte general-purpose area ? 3,968-byte general-purpose area general-purpose area (16 bytes) general-purpose area (3,968 bytes) vector address area (16 bytes) instruction reference area (96 bytes) 0000h 000fh 0010h 001fh 0020h 007fh 0080h fffh 7 6 5 4 3 2 1 0 reset 0000h 000ch 000ah 0008h 0006h 0004h 0002h intk intt0 ints int1 int0 intb/int4 figure 13 . rom address structure
s3c7254 product specification 4? 11 data memory (ram) in its standard configuration, the 512 x 4 -bit data memory has five areas: ? 32 4-bit working register area in bank 0 ? 224 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 176 4 -bit general-purpose area in bank 1 ? 80 4 -bit area for lcd data in bank 1 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses 0 0 0 h 0 1 f h 0 2 0 h 0 f f h 1 0 0 h 1 a f h f 8 0 h f f f h w o r k i n g r e g i s t e r s ( 3 2 x 4 b i t s ) m e m o r y - m a p p e d i / o a d d r e s s r e g i s t e r s ( 1 2 8 x 4 b i t s ) g e n e r a l - p u r p o s e r e g i s t e r s a n d s t a c k a r e a ( 2 2 4 x 4 b i t s ) g e n e r a l - p u r p o s e r e g i s t e r s ( 1 7 6 x 4 b i t s ) b a n k 1 5 b a n k 0 1 b 0 h l c d d a t a r e g i s t e r s ( 8 0 x 4 b i t s ) 1 f f h b a n k 1 figure 14. data memory (ram) map
product specification s3c7254 4? 12 addressing modes 1 . ' x ' m e a n s d o n ' t c a r e . 2 . b l a n k c o l u m n s i n d i c a t e r a m a r e a s t h a t a r e n o t a d d r e s s a b l e , g i v e n t h e a d d r e s s i n g m e t h o d a n d e n a b l e m e m o r y b a n k ( e m b ) f l a g s e t t i n g s h o w n i n t h e c o l u m n h e a d e r s . d a d a . b @ h l @ h + d a . b @ w x @ w l m e m a . b m e m b . @ l e m b = 0 e m b = 1 e m b = 0 e m b = 1 x x x 0 0 0 h w o r k i n g r e g i s t e r s b a n k 0 ( g e n e r a l r e g i s t e r s a n d s t a c k ) 0 1 f h 0 2 0 h 0 7 f h 0 8 0 h 0 f f h 1 0 0 h 1 a f h 1 b 0 h f 8 0 h f f f h b a n k 1 ( g e n e r a l r e g i s t e r s ) b a n k 1 ( d i s p l a y r e g i s t e r s ) b a n k 1 5 ( p e r i p h e r a l h a r d w a r e r e g i s t e r s ) f b 0 h f b f h f f 0 h f c 0 h s m b = 0 s m b = 1 s m b = 1 5 s m b = 1 s m b = 0 s m b = 1 s m b = 1 5 s m b = 1 r a m a r e a s a d d r e s s i n g m o d e n o t e s : 1 f f h figure 15 . ram address structure
s3c7254 product specification 4? 13 table 3 . i/o map for memory bank 15 memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 ? ? ? f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod .3 .2 .1 .0 w .3 (1) no yes f89h .7 "0" .5 .4 f8ah f8bh f8ch lmod .3 .2 .1 .0 w no no yes f8dh .7 .6 .5 .4 f8eh lcon .3 .2 "1" .0 w no yes no f8fh f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h "0" toe0 "0" "0" r/w yes yes no f93h f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h ? ? ? fa6h pne1 .3 .2 .1 .0 w no yes no fa7h
product specification s3c7254 4? 14 table 3 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fa8h pne2 .3 .2 .1 .0 w no no yes fa9h .7 .6 .5 .4 faah pne3 "0" .2 .1 .0 yes no ? ? ? fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c (2) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 .3 "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w no yes no fb6h imodk "0" .2 .1 .0 w no yes no fb7h scmod .3 "0" "0" .0 w yes no no fb8h ie4 irq4 ieb irqb r/w yes yes no fb9h fbah "0" "0" iew irqw r/w yes yes no fbbh "0" "0" iek irqk fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 yes fc3h bsc3 ? ? ?
s3c7254 product specification 4? 15 table 3 . i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fd0h clmod .3 "0" .1 .0 w no yes no fd1h fd2h fd3h fd4h cmpreg .3 .2 .1 .0 r no yes no fd5h fd6h cmod .3 .2 .1 .0 r/w no no yes fd7h .7 .6 .5 "0" fd8h fd9h fdah imod2 "0" "0" "0" .0 w no yes no fdbh fdch pumod1 .3 .2 "0" .0 w no no yes fddh "0" "0" "0" .4 fdeh pumod2 .3 .2 .1 .0 w no yes no fdfh fe0h smod .3 .2 .1 .0 w .3 no yes fe1h .7 .6 .5 "0" fe2h p1mod "0" "0" .1 .0 w no yes no fe3h fe4h sbuf r/w no no yes fe5h fe6h pmg1 .3 .2 .1 .0 w no no yes fe7h "0" .6 .5 .4 fe8h pmg2 .3 .2 .1 .0 fe9h .7 .6 .5 .4 ? ? ?
product specification s3c7254 4? 16 table 3 . i/o map for memory bank 15 (concluded) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit ff0h port 0 (p0) .3 .2 .1 .0 r/w yes yes no ff1h port 1 (p1) .3 .2 .1 .0 r ff2h port 2 (p2) .3 .2 .1 .0 r/w yes yes yes ff3h port 3 (p3) .3 / .7 .2 / .6 .1 / .5 .0 / .4 r/w ff4h port 4 (p4) "0" .2 .1 .0 r/w yes yes no ? ? ? fffh notes: 1. bit 3 in the wmod register is read only. 2. the carry flag can be read or written by specific bit manipulation instructions only.
s3c7254 product specification 4? 17 oscillator circuits the s3c7254 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. the main system clock frequencies can be divided by 4, 8, or 64 b y manipulating pcon bits 1 and 0 . the system clock mode control register, scmod, lets you select a main system clock (fx) or a subsystem clock (fxt) as the cpu clock and to start (or stop ) main system clock oscillation. the watch timer, buzzer and lcd display operate normally with a subsystem clock source, since they operate at very slow speeds and with very low power consumption (as low as 122 s at 32.768 khz). xin xout oscillator stop cpu clock wait release signal pcon.3,2 clear fxt selector fx watch timer fxx cpu stop signal (idle mode) lcd controller idle stop lcd controller basic timer timer/counters 0 serial i/o interface watch timer clock output circuit xin xout subsystem oscillator circuit main system oscillator circuit scmod.3 scmod.0 frequency dividing circuit 1/2 1/16 selector pcon.3 power-down release signal internal reset signal pcon.0 pcon.2 pcon.1 oscillator control circuit 1/4 figure 16 . clock circuit diagram
product specification s3c7254 4? 18 main system oscillator circuits xin xout figure 17 . crystal/ceramic oscillator (fx) xtin xtout external clock figure 18 . external oscillator (fx) xin xout r figure 19 . rc oscillator (fx) subsystem oscillator circuits 32.768 khz xtin xtout figure 20 . crystal/ceramic oscillator (fxt) xin xout figure 21 . external oscillator (fxt)
s3c7254 product specification 4? 19 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon bits 3 and 2 are addressed by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. there are two basic choices: ? main system clock (fx) or subsystem clock (fxt); ? divi ded fx frequency of 4, 8, or 64. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0" the main system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the subsystem clock is selected. table 4 . power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 if scmod.0 = "0" if scmod.0 = "1" 0 0 fx/64 ? 1 0 fx/8 ? 1 1 fx/4 fxt/4 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
product specification s3c7254 4? 20 instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main system clock (fx) or a subsystem clock (fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 5 shows corresponding cycle times in microseconds. table 5 . instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time (sec) fx/64 65.5 khz fx = 4.19 mhz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 fxt/4 8.19 khz fxt = 32.768 khz 122.0 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main system clock oscillation. only its least significant and most significant bits can be manipulated by 1-bit write instructions. subsystem clock oscillation cannot, of course, be stopped internally. also, if you have selected fx as the cpu clock, setting scmod.3 to "1" will not stop main system clock oscillation. this can only be done by a stop instruction. table 6. system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.0 cpu clock fx oscillation 0 0 fx on 0 1 fxt on 1 1 fxt off
s3c7254 product specification 4? 21 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, de termine whether a main system or a subsystem clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and subsystem clocks and to modify op erating frequencies. scmod.3 and scmod.0 select the main system clock (fx) or a subsystem clock (fxt) and start or stop main system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx or fxt clock by 4, 8, or 64. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 sec at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6?4 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect. table 7. elapsed mach i ne cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 8 machine cycles n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 16 machine cycles n/a fx / 4fxt pcon.0 = 1 scmod.0 = 1 n/a n/a fx / 4fxt (m/c) n/a notes : 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, the stop mode is not entered. 2. since the xin input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" when an external clock is used as the main system clock. 3. when the system clock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6 ?4. 4. 'n/a' means 'not available'.
product specification s3c7254 4? 22 + + programming tip ? switching between main system and subsystem clock 1. switch from the main system clo ck to the subsystem clock: ma2sub bits scmod.0 ; switches to subsystem clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the subsystem clock to the main system clock: sub2ma bitr scmod.3 ; start main system clock oscillation call dly80 ; delay 80 machine cycles bitr scmod.0 ; switch to main system clock ret
s3c7254 product specification 4? 23 clock output mode register (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4- bit write instructions only. reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6? 5. clock output mode register (clmod) organization table 8. clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, f x/64, fxt/4) 1.05 mhz, 524 khz, 65.5 khz , 8.19 khz 0 1 fxx/8 524 khz , 4.096 khz 1 0 fxx/16 262 khz , 2.048 khz 1 1 fxx/64 65.5 khz , 0.512 khz clmod.3 result of clmod.3 setting 0 clock output is disabled 1 clock output is enabled note : frequencies assume that fxx is 4.19 mhz and fxt is 32.768 khz . p m 4 . 0 p 4 . 0 o u t p u t l a t c h c l o c l m o d . 3 c l m o d . 2 c l m o d . 1 c l m o d . 0 c l o c k s e l e c t o r c l o c k s 4 ( f x x / 8 , f x x / 1 6 , f x x / 6 4 , c p u c l o c k ) figure 22. clo output pin circuit diagram
product specification s3c7254 4? 24 + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,#10h ld pmg1,ea ; p4.0 ? output mode bitr p4.0 ; clear p4.0 output latch ld a,#9h ld clmod,a
s3c7254 product specification 4? 25 interrupts the s3c7254 has four external, three internal and two quasi interrupts. table 9 shows the conditions for each interrupt generation. the request flags that allow the interrupts to be generated are cleared to logic zero by hardware when the service routine is vectored. the quasi interrupt (int2, irqw) request flags must be cleared by software. iek iet0 ies ie1 ie0 ie4 ieb intb int4 ints # @ @ power-down mode release signal # = noise filtering circuit @ = edge detection circuit * when fxx/64 is selected as a sampling clock for int0, idle mode can be released by int0. iew ie2 imod2 int2 imodk imod1 imod0 interrupt control unit vector interrupt generator ime ipr is1 is0 * irqb irq2 irqw irqk irqt0 irqs irq1 irq0 irq4 int1 int0 intw intt0 @ @ figure 23. interrupt control circuit diagram
product specification s3c7254 4? 26 table 9 . interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and-re - ceive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intk e when a rising or falling edge detected at any one of the k0?k3 pins 6 irqk int2 * e rising or falling edge detected at int2 ? irq2 intw i time in terval of 0.5 second or 3.19 ms ? irqw note : the quasi-interrupt int2 is only used for testing incoming signals. interrupt enable flags (iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 10. interrupt enable and request flag address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah 0 0 iew irqw fbbh 0 0 iek irqk fbch 0 0 iet0 irqt0 fbdh 0 0 ies irqs fbeh ie1 irq1 ie0 irq0 fbfh 0 0 ie2 irq2 notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode. interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4- bit write instructions, all interrupts must first be disabled by a di instruction. by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source.
s3c7254 product specification 4? 27 table 11 . standard interrupt priorities interrupt default priority intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intk 6 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 12 . interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 process all interrupt requests at low priority (note) 0 0 1 process intb and int4 interrupts only 0 1 0 process int0 interrupts only 0 1 1 process int1 interrupts only 1 0 0 process ints interrupts only 1 0 1 process intt0 interrupts only 1 1 0 process intk interrupts only note : when all interrupts are low priority (the lower three bits of the ipr register are logic zero), the interrupt requested first will have high priority. therefore, the first- request interrupt cannot be superceded by any other interrupt. external interrupt 0, 1 and 2 mode registers (imod0, imod1 and imod2) the following components are used to process external interrupts at the int0, int1 and int2 pins: ? noise filtering circuit for int0 ? edge detection circuit ? three mode registers, imod0, imod1 and imod2 the mode registers are used to control the triggering edge of the input signal. imod0, imod1 and imod2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. the int4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. since int2 is a qusi- interrupt, the interrupt request flag (irq 2) must be cleared by software. imod0, imod1 and imod2 are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests.
product specification s3c7254 4? 28 table 13. imod0, 1 and 2 register organization imod0 imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 select cpu clock for sampling 1 select fxx/64 sampling clock 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 imod2 0 0 0 imod1.0 imod2.0 effect of imod1 and imod2 settings 0 rising edge detection 1 falling edge detection when a sampling clock rate of fxx/64 is used for int0, an interrupt request flag must be cleared before 16 ma - chine cycles have elapsed. since the int0 pin has a clock-driven noise filtering circuit built into it, please take the following precautions when you use it: ? to trigger an interrupt, the input signal width at int0 must be at least two times wider than the pulse width of the clock se lected by imod0. this is true even when the int0 pin is used for general-purpose input. ? you can use int0 to re lease idle mode, when fxx/64 is selected as a sampling clock.
s3c7254 product specification 4? 29 int0 cpu clock fxx/64 int2 noise filter edge detection irq0 imod0 imod2 clock selector p1.2 p1.0 edge detection irq1 int1 p1.1 edge detection imod1 irq2 2 figure 24. circuit diagram for int0, int1 and int2 pins
product specification s3c7254 4? 30 external key interrupt mode register (imodk) the mode register for external key interrupts at the k0 ?k3 pins, imodk, is addressable only by 4-bit write instructions. reset clears all imodk bits to logic zero. rising or falling edge can be detected by bit imodk.2 settings. if a rising or falling edge is detected at any one of the selected k pin by the imodk register, the irqk flag is set to logic one and a release signal for power-down mode is generated. table 14. imodk register bit settings imodk 0 imodk.2 imodk.1 imodk.0 effect of imodk settings 0, 1 0 0 disable key interrupt 0 1 enable edge detection at the k0?k1 pins 1 0 enable edge detection at the k0?k2 pins 1 1 enable edge detection at the k0?k3 pins imodk.2 0 falling edge detection 1 rising edge detection note: 1. to generate a key interrupt, the selected pins must be configured to input mode. if any one pin of the selected pins is configured to output mode, only falling edge can be detected. 2. to generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. and then, select edge detection and pins by setting imodk register. p 0 . 3 / k 3 p 0 . 2 / k 2 p 0 . 1 / k 1 p 0 . 0 / k 0 i m o d k p i n s e l e c t o r i r q k r i s i n g / f a l l l i n g e d g e s e l e c t o r figure 25. circuit diagram for intk
s3c7254 product specification 4? 31 power-down the s3c7254 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. in stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, serial i/o, timer/ counter 0, watch timer, and lcd controller ? and on external interrupt requests, is detailed in table 15. table 15. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) system clock status can be changed only if the main system clock is used can be changed if the main system clock or subsystem clock is used clock oscillator main system clock oscillation stops cpu clock oscillation stops (main and subsystem clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial i/o interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates watch timer operates only if subsystem clock (fxt) is selected as the counter clock watch timer operates lcd controller operates only if a subsystem clock is se - lected as lcdck lcd controller operates external interrupts int1, int2, int4, and intk are acknowledged; int0 is not serviced int1, int2, int4, int0, and intk are acknowledged (note) cpu all cpu operations are disabled all cpu operations are disabled mode release signal interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input interrupt request signals are enabled by an interrupt enable flag or by reset input (note) note : int0 can be operated in idle mode only when fxx/64 is selected as a sampling clock.
product specification s3c7254 4? 32 + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system clock ? subsystem clock switch subroutine smb 15 ld ea,#00h ld p2,ea ; all key strobe outputs to low level ld a,#3h ld imodk,a ; select k0 ?k3 enable smb 0 bitr irqw bitr irqk bits iew bits iek clks1 call watdis ; execute clock and display changing subroutine btstz irqk jr cidle call sub2ma ; subsystem clock ? main system clock switch subroutine ei ret cidle idle ; engage idle mode nop nop jps clks1
s3c7254 product specification 4? 33 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 16 . table 16 . unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0 / sck / k0 p0.1 / so / k1 p0.2 / si / k2 p0.3 / buz / k3 input mode: connect to v dd output mode: no connection p1.0 / cin0 / int0 p1.1 / cin1 /int1 p1.2 / int2 p1.3 / int4 connect to v dd (1) p2.0?p2.3 input mode: connect to v dd output mode: no connection p3.0?p3.1 p3.2 / lcdsy p3.0 / lcdck p4.0 / clo p4.1 / tcl0 p4.2 / tclo0 input mode: connect to v dd output mode: no connection p5.0 / seg32?p5.7 / seg39 no connection (2) seg0?seg29 seg30?seg31 com0?com7 no connection v lc1 ?v lc5 no connection xt in connect xt in to v ss or v dd xt out no connection test connect to v ss notes 1. digital mode at p1.0 and p1.1 2. used as segment
product specification s3c7254 4? 34 reset reset table 17 provides detailed information about hardware register values after a reset occurs during power-down mode or during normal operation. table 17. hardware register values after reset reset hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower six bits of address 0000h are transferred to pc11?8, and the contents of 0001h to pc7?0. lower six bits of address 0000h are transferred to pc11?8, and the contents of 0001h to pc7?0. bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?bsc3) 0 0 program status word (psw): carry flag (c) retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): working registers e, a, l, h, x, w, z, y values retained undefined general-purpose registers values retained (note) undefined clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock mode register (scmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 intk mode register (imodk) 0 0 note : the values of the 0f8h-0fdh are not retained when a reset signal is input.
s3c7254 product specification 4? 35 table 17 . hardware register values after reset reset (continued) hardware component or subcomponent if reset reset occurs during power-down mode if reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod1/2) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 timer/counters 0 and 1: count registers (tcnt0) 0 0 reference registers (tref0) ffh ffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off serial i/o interface: sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined n-channel open-drain mode register pne1/2/3 0 0 comparator comparator mode register (cmod) 0 0 comparison result register undefined undefined
product specification s3c7254 4? 36 i/o ports the s3c7254 has 6 ports. there are total of 4 input pins, 8 output pin and 15 configurable i/o pins, for a maximum number of 27 pins. port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 18 . port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe6h pm0.3 pm0.2 pm0.1 pm0.0 fe7h "0" pm4.2 pm4.1 pm4.0 pmg2 fe8h pm2.3 pm2.2 pm2.1 pm2.0 fe9h pm3.3 pm3.2 pm3.1 pm3.0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit ="1", the pin i s set to output mode: pm0.0 for p0.0, pm0.1 for p0.1, etc,. all flags are cleared to logic zero following reset . + + programming tip ? configuring i/o ports to input or output configure ports 0 and 2 as an output port: bits emb smb 15 ld ea,#7fh ld pmg1,ea ; p0 and p4 ? output
s3c7254 product specification 4? 37 port 1 mode register (p1mod) p1mod register settings determine if port 1 is used for digital input or for analog input. the p1mod register is a 4-bit write only register. p1mod is mapped to address fe2h. a reset operation initializes all p1mod values to logic zero, configuring port 1 as an analog input port. when a p1mod bit is "0", the corresponding pin is configured as a analog input pin. when set to "1", it is configured as an digital input pin: p1mod.0 correspond s to p1.0, and p1mod.1 to p1.1. note int0 and int1 can occur only when the port is configured to digital input. if you change the input mode from digital to analog using p1mod settings, irq0 and irq1 will be set. when you use analog input, you must clear the corresponding interrupt enable flag (iex). that is, clear ie0 when p1.0 is an analog input and clear ie1 when p1.1 is an analog input. pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod1 and pumod2) are used to assign internal pull-up resistors by soft ware to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. table 19 . pull-up resistor mode register (pumod) organization pumod id address bit 3 bit 2 bit 1 bit 0 pumod1 fdch pur3 pur2 ?0? pur0 fddh 0 0 0 pur4 pumod2 fdeh pur1.3 pur1.2 pur1.1 pur1.0 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pur3 for port 3, pur2 for port 2, and so on. + + programming tip ? enabling and disabling i/o port pull-up resistors p6 and p7 enable pull-up resistors. bits emb smb 15 ld ea,#0ch ld pumod1,ea ; p2 and p3 enable n-channel open-drain mode register the n-channel open-drain mode register (pne) is used to configure ports 0, 2, 3 and 4 to n-channel open-drain or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel, open-drain; when set to "0", the output pin is configured to push-pull. the pne register consists of an 8-bit register and a 4-bit register; pne1 and pne3 can be addressed by 4-bit write instructions only and pne2 by 8-bit write instructions only. pne id address bit 3 bit 2 bit 1 bit 0 pne1 fa6h p0.3 p0.2 p0.1 p0.0 pne2 fa8h p2.3 p2.2 p2.1 p2.0 fa9h p3.3 p3.2 p3.1 p3.0 pne3 faah 0 p4.2 p4.1 p4.0
product specification s3c7254 4? 38 port 0 circuit diagram p0.0 / sck /k0 p0.1 /so /k1 p0.2 /si /k2 output latch m u x pur0 v dd when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: p0.3 /buz /k3 cmos push- pull or n-channel open-drain 1, 4 1, 4 pne1.3 pne1.2 pne1.1 pne1.0 pm0.2 pm0.1 pm0.0 pm0.3 figure 26 . port 0 circuit diagram
s3c7254 product specification 4? 39 port 1 circuit diagram int0 int1 int2 int4 p1.0 /int0 /cin0 p1.1 /int1 /cin1 p1.2 / int2 p1.3 / int4 v dd v dd v dd n/r circuit n/r = noise reduction imod0 v dd pur1.0 pur1.3 pur1.2 pur1.1 digital input analog input external reference digital input analog input digital input digital input figure 27 . input port 1 circuit diagram
product specification s3c7254 4? 40 ports 2 and 3 circuit diagram px.b purx when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: 1, 4, 8 1, 4, 8 x = 2, 3 b = 0, 1, 2, 3 m u x output latch pne2 pmx.b v dd figure 28 . ports 2 and 3 circuit diagram
s3c7254 product specification 4? 41 port 4 circuit diagram p4.0 /clo p4.1 /tcl0 p4.2 /tclo0 m u x pur3 v dd when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). note: cmos push-pull or n-channel open-drain pne3.2 pne3.1 pne3.0 pm4.2 pm4.1 pm4.0 1, 4 1, 4 output latch figure 29. port 4 circuit diagram
product specification s3c7254 4? 42 basic timer (bt) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . interval timer function the measurement of elapsed time intervals is the basic timer's primary function. the standard interval is 256 bt clock pulses. to restart the basic timer, set bit 3 of the mode register bmod to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2?bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs. an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is then generated, bcnt is cleared to logic zero, and counting continues from 00h. oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when power-down mode is released by an interrupt. when a reset signal is generated , the standard stabilization interval for system clock oscillation following a reset is 31.3 ms at 4.19 mhz. "clear" signal bits instruction bmod.3 bmod.2 bmod.1 bmod.0 clock selector bcnt irqb interrupt request overflow cpu clock start signal (power-down release) 1-bit r/w clock input (fxx/2 12 , fxx/2 9 , fxx/2 7 , fxx/2 5 ) clear irqb 4 clear bcnt 8 figure 30 . basic timer circuit diagram
s3c7254 product specification 4? 43 basic timer mode register (bmod) the basic timer mode register, bmod, is used to select the input frequency and the oscillation stabilization time. the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one (enabled) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation is restarted. table 20 . basic timer mode register (bmod) organization bmod.3 basic timer restart bit 1 restart basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock oscillation stabilization 0 0 0 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 1 0 1 fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes : 1. cl ock frequencies and stabilization intervals assume a system oscillator clock frequency (fxx) of 4.19 mhz. 2. fxx = selected system clock frequency. 3. oscillation stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time." 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz. basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. when bcnt has incremented to hexadecimal 'ffh' (255 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met.
product specification s3c7254 4? 44 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cp se ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop normal operating mode stop mode idle mode (31.3 ms) cpu operation stop instruction stop mode is released by interrupt normal operating mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
s3c7254 product specification 4? 45 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. tcl0 tclo0 serial i/o clear inverted clear set clear clocks (fxx/2 10 , fxx/2 6 , fxx/2 4 , fxx) 8 8 8 tmod0.0 tmod0.1 tmod0.2 tmod0.3 tmod0.4 tmod0.5 tmod0.6 tmod0.7 tcnt0 8-bit comparator tol0 p4.2 latch toe0 irqt0 pm4.2 clock selector tref0 figure 31 . tc0 circuit diagram
product specification s3c7254 4? 46 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4? tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, p4.1/tcl0 must be set to input mode. . table 20-1 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges tc0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p4.2 must be set to output mode ("1") ? output latch value for p4.2 must be set to "0" + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,#40h ld pmg1,ea ; p4.2 ? output mode bitr p4.2 ; p4.2 clear bits toe0
s3c7254 product specification 4? 47 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. table 21 . tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero tmod0.6 f91h tmod0.5 0,1 specify input clock edge and internal frequency tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (t his bit is automatically cleared to logic zero immediately after counting resumes.) tmod0.2 0 disable timer/counter 0; retain tcnt0 contents f90h 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero table 22 . tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx = 4.19 mhz note : 'fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4.09 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
product specification s3c7254 4? 48 tc0 reference register (tref0) tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from ti mer/counter 0 to the tclo0 pin. (msb) (lsb) f92h ?0? toe0 "0" "0" when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea
s3c7254 product specification 4? 49 watch timer watch timer functions include real-time and watch- time measurement and interval timing for the main and sub system clock. it is also used as a clock source for the lcd controller and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register (wmod.2) to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a main system or subsystem clock source the watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal (fxt) as its source; if wmod.0 = "0", the main system clock (fx) is used as the signal source, according to the following for - mula: watch timer clock (fw) = main system clock (fx) 128 = 32.768 khz (fx = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock (fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. clock source generation for lcd controller the watch timer supplies the clock frequency for the lcd controller (f lcd ). therefore, if the watch timer is dis abled, the lcd controller does not operate. buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to select the desired buz frequency , load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 0.3 is cleared to "0" ? the port 0.3 output mode flag (pm0.3) set to 'output' mode timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high-speed mode is useful for timing events for program debugging sequences. check subsystem clock level feature the watch timer can also check the input level of the subsystem clock by testing wmod.3. if wmod.3 is "1", the input level at the xt in pin is high; if wmod.3 is "0", the input level at the xt in pin is low.
product specification s3c7254 4? 50 f x = m a i n s y s t e m c l o c k ( 4 . 1 9 m h z ) f x t = s u b s y s t e m c l o c k ( 3 2 . 7 6 8 k h z ) f w = w a t c h t i m e r f r e q u e n c y w m o d . 7 w m o d . 6 w m o d . 5 w m o d . 4 w m o d . 3 w m o d . 2 w m o d . 1 w m o d . 0 8 p 0 . 3 l a t c h p m 0 . 3 f r e q u e n c y d i v i d i n g c i r c u i t s e l e c t o r c i r c u i t i r q w f x t f x / 1 2 8 f w 3 2 . 7 6 8 k h z b u z m u x f w / 2 7 f w / 2 ( 2 h z ) 1 4 e n a b l e / d i s a b l e c l o c k s e l e c t o r l c d f f w / 1 6 ( 2 k h z ) f w / 8 ( 4 k h z ) f w / 4 ( 8 k h z ) f w / 2 ( 1 6 k h z ) figure 32 . watch timer circuit diagram
s3c7254 product specification 4? 51 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. table 23 . watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output 1 enable buzzer (buz) signal output wmod.6 0 always logic zero wmod.5 ? .4 0 0 2 khz buzzer (buz) signal output f89h 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low 1 input level to xt in pin is high wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer f88h wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select (fx/128 ) as the watch timer clock (fw) 1 select subsystem clock as watch timer clock (fw) note : main system clock frequency (fx) is assumed to be 4.19 mhz; subsystem clock (fxt) is assumed to be 32.768 khz. + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second int errupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#8h ld pmg1,ea ; p0.3 ? output mode bitr p0.3 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
product specification s3c7254 4? 52 lcd controller/driver the s3c7254 microcontroller can directly drive an up-to-320?dot (40 segments x 8 commons) lcd panel. data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. lcd ram address area ram addresses of bank 1 are used as lcd data memory. these locations can be addressed by 1-bit, 4-bit, or 8-bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?seg40 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general- purpose use. s e g 0 com0 com1 com2 com3 com4 com5 com6 com7 b0 b1 b2 b3 b0 b1 b2 b3 1b0h 1b1h 1b2h 1b4h 1fch 1feh 1b3h 1b5h 1fdh 1ffh s e g 1 s e g 2 s e g 3 8 s e g 3 9 ...... figure 33 . lcd display data ram organization table 24 . common and segment pins per duty cycle duty common pins segment pins dot number 1/8 com0?com7 32?40 pins 256 dots?320 dots 1/4 com0?com3 128 dots?160 dots 1/3 com0?com2 96 dots?120 dots 1-bit output the eight output pins (p5.0-p5.7) of the 40-segment output pins can be set in 4 bits for 1-bit level output by lmod.6 and lmod.7. at this time, the bit 0 of the even addressed display ram is used as the output latch of 1- bit output pins. the 1f0h.0 in lcd display ram is used as the output latch for p5.0, 1f2h.0 is for p5.1,?? and 1feh.0 is for p5.7. these 1-bit output pins cannot be used as 4 bits and 8 bits.
s3c7254 product specification 4? 53 lcd circuit diagram com7 v lc5 l cdsy l cdck pm3.3 p3.2 latch display ram (bank"1") mux seg39 / p5.7 seg0 seg31 f lcd selector 80 40 data bus seg32 / p5.0 timing controller lmod lcon com control lcd voltage control com0 v lc1 p3.3 latch pm3.2 figure 34 . lcd circuit diagram
product specification s3c7254 4? 54 lcd control register (lcon) the lcd control register (lcon) is used to turn the lcd display on and off, to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion, and to control the flow of current to dividing resistors in the lcd circuit. the effect of the lcon.0 setting is dependent upon the current setting of bits lmod.0 and lmod.1. table 25 . lcd control register (lcon) organization lcon bit setting description lcon.3 0 1/4 bias select 1 1/3 bias select lcon.2 0 disable lcdck and lcdsy signal outputs. 1 enable lcdck and lcdsy signal outputs. lcon.1 , lcon.0 0,0 lcd display off 1,0 lcd display on when using an external resistor for contrast control . 1 ,1 lcd display on when not using an external resistor for contrast control. notes : 1. in case of lcon.0, you should turn on/off ?lcd display? using internal resistor. if you want to turn on/off lcd or to control ?lcd contrast?? internally, you should set the lcon.0 to ?0?. 2. to select lcd bias, you must use both the lcon.3 setting and an external lcd bias circuit connection. 3. if you turn the lcd display off (lcon.0 = "0"), you reduce the current flowing through the lcd dividing resistor rs. table 26 . lmod.1?0 bits settings lmod.1?lmod.0 com0?com 7 seg0?seg39 seg32/p5.0?seg39/p5.7 power supply to the dividing resistor 0, 0 all of the lcd dots off 1-bit output function on 0, 1 all of the lcd dots on 1, 0 common and segment signal output corresponds to display data (normal display mode)
s3c7254 product specification 4? 55 lcd mode register (lmod) the lcd mode control register lmod is used to control display mode; lcd clock, segment or port output, and display on/off. lmod can be manipulated using 8-bit write instructions. the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency. since lcdck is generated by dividing the watch timer clock (fw), the watch timer must be enabled when the lcd display is turned on. the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. the lcd mode register lmod controls the output mode of the 8 pins used for normal outputs (p5.0?p5.7). bits lmod.7?5 define the segment output and normal bit output configuration. table 27 . lcd clock signal (lcdck) frame frequency lcdck 128 hz 256 hz 512 hz 1024 hz 2048 hz 4096 hz display duty cycle 1/8 ? ? 64 hz 128 hz 256 hz 512 hz 1/4 ? 64 hz 128 hz 256 hz 512 hz ? 1/3 42.7 hz 85.3 hz 170.7 hz 341.3 hz ? ? note: fw = 32.768 khz 1 frame com0
product specification s3c7254 4? 56 table 28 . lcd mode register (lmod) organization segment /output port selection bits lmod.7 lmod.6 seg39?36 seg35?32 total number of segment 0 0 seg port seg port 40 0 1 seg port output port 36 1 0 output port seg port 36 1 1 output port output port 32 lcd clock selection bits lmod.5 lmod.4 lcd clock (lcdck) 1/8 duty (com0?com7) 1/4 duty (com0?com3) 1/3 duty (com0?com2) 0 0 f w / 2 6 (512 hz) f w / 2 7 (256 hz) f w / 2 8 (128 hz) 0 1 f w / 2 5 (1024 hz) f w / 2 6 (512 hz) f w / 2 7 (256 hz) 1 0 f w / 2 4 (2048 hz) f w / 2 5 (1024 hz) f w / 2 6 (512 hz) 1 1 f w / 2 3 (4096 hz) f w / 2 4 (2048 hz) f w / 2 5 (1024 hz) note: lcdck is supplied only when the watch timer operates. to use the lcd controller, bit 2 in the watch mode register wmod should be set to 1. duty selection bits lmod.3 lmod.2 duty 0 0 1/8 duty (com0?com7 select) 1 0 1/4 duty (com0?com3 select) 1 1 1/3 duty (com0?com2 select) display mode selection bits lmod.1 lmod.0 function 0 0 all lcd dots off 0 1 all lcd dots on 1 0 normal display
s3c7254 product specification 4? 57 lcd voltage dividing resistors on-chip voltage dividing resistors for the lcd drive power supply can be configured by mask option to the v lc1 ?v lc5 pins. power can be supplied without an external dividing resistor. figure 12?4 shows the bias connections for the s3c7254 lcd drive power supply. 1/3 bias vlc1 vlc2 vlc3 vlc4 vlc5 1/4 bias vlc1 vlc2 vlc3 vlc4 vlc5 KS57C2504 KS57C2504 figure 35 . lcd bias circuit connection s3c7254 s3c7254
product specification s3c7254 4? 58 application without contrast control if you use an internal transistor (lcon.0) to turn on/off 'lcd display', you can get a merit that peripheral circuits are simple. but in that case, you can't control lcd contrast. application with internal resistor KS57C2504 v lc1 v lc2 v lc3 v lc4 v lc5 v ss lcon.0 (3) v dd application with external resistor KS57C2504 lcon.0 (3) v lc1 v lc2 v lc3 v lc4 v ss v dd v dd mask option v lc5 v lcd n: 1, 2, 3, 4, 5 com & seg v dd or v lcn lcd data out v ss or v lcn lcon.1 n: 1, 2, 3, 4, 5 com & seg v dd or v lcn lcd data out v ss or v lcn lcon.1 figure 36 . connection for lcd on/off using internal transistor notes: 1. a 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for figure 35. 2. when you turn off the lcd display using lcon settings, the amount of current flowing through the dividing resistors is reduced more than when you use lmod to turn off the display. 3. when lcon.0?.1 = #00b, lcd display is turned off. when lcon.0?.1 = #11b, lcd display is turned on. s3c7254 s3c7254
s3c7254 product specification 4? 59 application with contrast control if you turn on/off 'lcd display' using external output pin, you can control lcd contrast using variable resistor. application with internal resistor KS57C2504 v lc1 v lc2 v lc3 v lc4 v lc5 v ss lcon.0 (always "0") v dd px.b (3) vr application with external resistor KS57C2504 lcon.0 (always "0") v lc1 v lc2 v lc3 v lc4 v ss v dd v dd mask option v lc5 vr px.b (3) n: 1, 2, 3, 4, 5 com & seg v dd or v lcn v ss or v lcn n: 1, 2, 3, 4, 5 com & seg v dd or v lcn v ss or v lcn v lcd lcd data out lcon. 1 lcd data out lcon. 1 figure 37 . connection for lcd on/off using external output pin notes : 1. a 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for figure 35 . 2. when you turn off the lcd display using lcon settings, the amount of current flowing through the dividing resistors is reduced more than when you use lmod to turn off the display. 3. when lcon.0?.1 = #00b and px.b = #1b, lcd display is turned off. when lcon.0?.1 = #10b and p x.b = #0b, lcd display is turned on. s3c7254 s3c7254
product specification s3c7254 4? 60 common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/8 duty mode, com0 ?com7 pins are selected ? in 1/4 duty mode, com0 ?com3 pins are selected ? in 1/3 duty mode, com0 ?com2 pins are selected segment (seg) signals the 40 lcd segment signal pins are connected to corresponding display ram locations at bank 1. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
s3c7254 product specification 4? 61 c o m 0 v d d f r v s s 1 f r a m e 0 1 2 3 v d d c o m 0 v l c 1 v l c 2 v l c 4 v l c 5 4 5 6 7 0 1 2 3 4 5 6 7 ( v l c 3 ) v d d c o m 1 v l c 1 v l c 2 v l c 4 v l c 5 ( v l c 3 ) v d d c o m 2 v l c 1 v l c 2 v l c 4 v l c 5 ( v l c 3 ) v d d s e g 0 v l c 1 v l c 2 v l c 4 v l c 5 ( v l c 3 ) + v l c d s e g 0 ? c o m 0 + 1 / 4 v l c d - v l c d c o m 1 c o m 2 c o m 3 c o m 4 c o m 5 c o m 6 c o m 7 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 0 v - 1 / 4 v l c d figure 38 . lcd signal waveforms (1/8 duty, 1/4 bias)
product specification s3c7254 4? 62 v dd fr v ss 1 frame 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 + v lcd seg1?com0 ?v lcd v dd seg1 v lc1 v lc4 v lc5 0 v v lc2 (v lc3 ) +1/4 v lcd -1/4 v lcd figure 39. lcd signal waveforms (1/8 duty, 1/4 bias) (continued)
s3c7254 product specification 4? 63 c o m 0 ? s e g 0 c o m 3 c o m 2 c o m 1 c o m 0 0 1 2 3 0 1 2 3 s e g 0 s e g 1 v d d v s s v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 v d d v l c 1 ( v l c 2 ) v l c 3 ( v l c 4 ) v l c 5 + v l c d + 1 / 3 v l c d 0 v - 1 / 3 v l c d - v l c d c o m 0 c o m 1 c o m 2 c o m 3 s e g 1 s e g 0 1 f r a m e figure 40. lcd signal waveforms (1/4 duty, 1/3 bias)
product specification s3c7254 4? 64 com0?seg0 com2 com1 com0 seg0 seg1 v dd v ss v dd v lc1 (v lc2 ) v lc3 (v lc4 ) v lc5 v dd v lc1 (v lc2 ) v lc3 (v lc4 ) v lc5 v dd v lc1 (v lc2 ) v lc3 (v lc4 ) v lc5 v dd v lc1 (v lc2 ) v lc3 (v lc4 ) v lc5 v dd v lc1 (v lc2 ) v lc3 (v lc4 ) v lc5 + v lcd +1/3 v lcd 0 v -1/3 v lcd - v lcd 0 1 2 0 1 2 1 frame com0 com1 com2 seg2 seg1 seg0 figure 41. lcd signal waveforms (1/3 duty, 1/3 bias)
s3c7254 product specification 4? 65 comparator p1.0 and p1.1 can be used as a analog input port for a comparator. the reference voltage for the 2 - channel comparator can be supplied either internally or externally at p1.0. when an internal reference voltage is used, two channels (p1.0?p1.1) are used for analog inputs and the internal reference voltage is varied in 16 levels. if an external reference voltage is input at p1.0, the other p1.1 pins are used for analog input. when a conversion is completed, the result is saved in the comparison result register cmpreg. the initial values of the cmpreg are undefined and the comparator operation is disabled by a reset . the comparator module has the following components: p1.0 /cin0 /int0 p1.1 /cin1 /int1 comparison result register (cmpreg) 8 m u x v dd 1/2r r r 1/2r cmod.7 cmod.6 cmod.5 0 cmod.3 cmod.2 cmod.1 cmod.0 v ref (internal) + ? internal bus m u x 4 m u x v ref (external) note: int occures only for digital input selecting: for analog input, any int doesn't. figure 42 . comparator circuit diagram
product specification s3c7254 4? 66 comparator mode register (cmod) the comparator mode register cmod is an 8-bit register that is used to select the operation mode of the comparator. 1: cin0; external reference, cin1; analog input 0: internal reference, cin0?1; analog input reference voltage (v ref ) selection: vdd x (n + 0.7)/16, n = 0 to 15 1: conversion time(4 x 2 4 /fx, 15.6 s @4.19mhz) 0: conversion time(4 x 2 7 /fx, 122.2 s @4.19mhz) 1: comparator operation enable 0: comparator operation disable fd6h?fd7h cmod.7 cmod.6 cmod.5 "0" cmod.3 cmod.2 cmod.1 cmod.0 figure 43 . comparator mode register (cmod) organization
s3c7254 product specification 4? 67 port 1 mode register (p1mod) p1mod register settings determine if p1.0 and p1.1 are used for analog or digital input. the p1mod register is 4-bit write-only register. p1mod is mapped to address fe2h. a reset operation initializes all p1mod register values to zero, configuring p1.0 and p1.1 as a analog input port. comparator operation the comparator compares analog voltage input at cin0 - cin1 with an external or internal reference voltage (v ref ) that is selected by the cmod register. the result is written to the comparison result register cmpreg at address fd4h. the comparison result at internal reference is calculated as follows: if "1" analog input voltage >= v ref + 150 mv if "0" analog input voltage <= v ref ? 150 mv to obtain a comparison result, the data must be read out from the cmpreg register after v ref is updated by changing the cmod value after a conversion time has elapsed. analog input voltage (cin0?1) reference voltage (v ref ) comparator clock (cmpclk, fx/16, fx/128) comparison result (cmpreg) comparison time (cmpclk x 4) comparison end 1 0 comparison start unknown 1 figure 44 . conversion characteristics + + programming tip ? programming the comparator the following code converts the analog voltage input at the cin0?cin1 pins into 4-bit digital code. bitr emb ld a,#3h ld p1mod,a ; analog input selection (cin0 ?cin1) ld ea,#0cxh ; x = 0 ?f, comparator enable ; internal reference, conversion time ( 15.6 s at 4.19 mhz) ld cmod,e a ld a,#0h wait incs a jr wait ld a,cmpreg ; read the result ld p2,a ; output the result from port 2
product specification s3c7254 4? 68 serial i/o interface using the serial i/o interface, 8-bit data can be exchanged with an external device. the transmission frequency is controlled by making the appropriate bit settings to the smod register. the serial interface can run off an internal or an external clock source, or the tol0 signal that is generated by the 8-bit timer/counter, tc0. if the tol0 clock signal is used, you can modify its frequency to adjust the serial data transmission rate. smod.7 smod.6 smod.5 ? smod.3 smod.2 smod.1 smod.0 clock selector tol0 p0.0 / sck q r s sbuf (8-bit) si so q d ck lsb or msb first r irqs 8 clear q0 q1 q2 3-bit counter 8 internal bus bits * * instruction excution internal bus overflow fxx/2 4 fxx/2 10 cpu clk figure 45 . serial i/o interface circuit diagram
s3c7254 product specification 4? 69 serial i/o mode register (smod) the serial i/o mode register, smod, is an 8-bit register that specifies the operation mode of the serial interface. its reset value is logical zero. smod is organized in two 4-bit registers, as follows: smod register settings enable you to select either msb-first or lsb-first serial transmission, and to operate in transmit-and-receive mode or receive- only mode. smod is a write-only register and can be addressed only by 8-bit ram control instructions. one exception to this is smod.3, which can be written by a 1-bit ram control instruction. when smod.3 is set to 1, the contents of the serial interface interrupt request flag, irqs, and the 3-bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to logical zero. table 29 . sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol0 clock from tc0 0 1 x cpu clock: fxx/4, fxx/8, fxx/64 enable sbuf read/write 1 0 0 4.09 khz clock: fxx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 1 1 1 262 khz clock: fxx/2 4 notes : 1. 'fxx' = system clock; 'x' means 'don't care.' 2. khz frequency ratings assume a system clock (fxx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fxx/2 4 clock if the cpu clock is fxx/64 .
product specification s3c7254 4? 70 serial i/o timing diagrams sck si so irqs di7 di6 di5 di4 di3 di2 di1 di0 do7 do6 do5 do4 do3 do2 do1 do0 transmit complete set smod.3 figure 46 . sio timing in transmit/receive mode high impedance sck si irqs transmit complete set smod.3 di7 di6 di5 di4 di3 di2 di1 di0 so figure 47 . sio timing in receive-only mode
s3c7254 product specification 4? 71 + + programming tip ? setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock frequency of fxx/2 4 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output ld ea,#48h ; ld sbuf,ea ; ld ea,#0eeh ld smod,ea ; sio data transfer external device sck / p0.0 so / p0.1 s3c7254 2. use cpu cl ock to transfer and receive serial data at high speed: bitr emb ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2 / si ? input ld ea,tdata ; tdata address = bank0 (20h?7fh) ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf ld rdata,ea ; rdata address = bank0 (20h?7fh)
product specification s3c7 254 4? 72 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode : bitr emb ld ea,#03h ld pmg1,ea ; p0.0 / sck and p0.1 / so ? output, p0.2/si ? input ld ea,tdata ; tdata address = bank0 (20h?7fh) ld sbuf,ea ld ea,#8fh ld smod,ea ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data, ; tdata address = bank0 (20h?7fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h ?7fh) bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2 s3c7254
s3c7254 product specification 4? 73 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 4. transmit and receive an external clock in lsb-first mode: bitr emb ld ea,#02h ld pmg1,ea ; p0.1 / so ? output, p0.0 / sck and p0.2 / si ? input ld ea,tdata ; tdata address = bank0 (20h?7fh) ld sbuf,ea ld ea,#0fh ld smod,ea ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data, ; tdata address = bank0 (20h?7fh) xch ea,sbuf ; transmit data ? receive data l d rdata,ea ; rdata address = bank0 (20h ?7fh) bits smod.3 ; sio start pop ea pop sb iret external device sck / p0.0 so / p0.1 si / p0.2 s3c7254 high speed sio transmission
product specification s3c7 254 4? 74 electrical data table 30 . absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 7.0 v input voltage v i1 all i/o ports ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o port active ? 15 ma all i/o ports active ? 30 output current low i ol one i/o port active + 30 (peak value) ma + 15 note all i/o port, total + 100 (peak value) + 60 note operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note : t he values for output current low ( i ol ) are calculated as peak value duty .
s3c7254 product specification 4? 75 table 31 . d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units input high voltage v ih1 ports 2, 3, p4.0 and p4.2 0.7 v dd ? v dd v v ih2 ports 0, 1, p4.1 and reset 0.8 v dd ? v dd v ih3 x in , x out and xt in v dd ? 0.5 ? v dd input low voltage v il1 ports 2, 3, p4.0 and p4.2 ? ? 0.3 v dd v v il2 ports 0, 1, p4.1 and reset ? ? 0.2 v dd v il3 x in , x out and xt in ? ? 0.4 output high voltage v oh1 v dd = 4.5 v to 6.0 v i oh = ? 3 ma ports 0, 2, 3 and 4 v dd ? 2.0 v dd ? 0.4 ? v v oh2 v dd = 4.5 v to 6.0 v i oh = ? 100 a port 5 v dd ? 2.0 ? ? output low voltage v ol1 v dd = 4.5 v to 6.0 v i ol = 15 ma ports 0, 2, 3 and 4 ? 0.4 2 v v ol2 v dd = 4.5 v to 6.0 v i ol = 100 a port 5 ? ? 1
product specification s3c7 254 4? 76 table 31 . d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units input high leakage current i lih1 v in = v dd all input pins except those specified below for i lih2 ? ? 3 a i lih2 v in = v dd x in , x out and xt in ? ? 20 a input low leakage current i lil1 v in = 0 v all input pins except x in , x out, xt in and reset ? ? ? 3 i lil2 v in = 0 v x in , x out , and xt in ? ? ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 pull-up resistor r l1 v in = 0 v; v dd = 5 v 10% ports 0?4 15 40 80 kw v dd = 3 v 10% 30 80 200 r l2 v in = 0 v; v dd = 5 v 10% reset 150 220 350 kw v dd = 3 v 10% 300 400 800 lcd voltage dividing resistor r lcd ? 40 55 90 kw i v dd -com i i voltage drop (i = 0?7) v dc v dd = 2.7 v to 6.0 v ? 15 a per common pin ? ? 120 mv i v dd -segx i voltage drop (x = 0?39) v ds v dd = 2.7 v to 6.0 v ? 15 a per segment pin ? ? 120 v lc1 output voltage v lc1 v dd = 3.5 v to 6.0 v (1) lcd clock = 0 hz, v lc5 = 0 v 0.8 v dd ? 0.15 0.8 v dd 0.8 v dd + 0.15 v v lc2 output voltage v lc2 0.6 v dd ? 0.15 0.6 v dd 0.6 v dd + 0.15 v lc3 output voltage v lc3 0.4 v dd ? 0.15 0.4 v dd 0.4 v dd + 0.15 v lc4 output voltage v lc4 0.2 v dd ? 0.15 0.2 v dd 0.2 v dd + 0.15
s3c7254 product specification 4? 77 table 31 . d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units supply (6 ) current i dd1 (2) v dd = 5 v 10% (3) 4.19 mhz crystal oscillator ? 2.7 8 ma v dd = 3 v 10% (4) 0.27 1.2 i dd2 (2) idle mode; v dd = 5 v 10% 4.19 mhz crystal oscillator ? 1.2 1.8 v dd = 3 v 10% 0.26 1.0 i dd3 (5) v dd = 3 v 10% 32 khz crystal oscillator ? 17 90 a i dd4 (5) v dd = 3 v 10% 32 khz crystal oscillator ? 6 15 a i dd5 stop mode; v dd = 5 v 10% ? 0.5 5 v dd = 3 v 10% 0.2 3 notes: 1. 1/5 bias for test only. in 1/4 bias lcd operation mode, v dd condition is 2.7 v to 6.0 v. 2. data includes power consumption for subsystem clock oscillation. 3. for high-speed controller operation, the power control register (pcon) must be set to 0011b. 4. for low-speed controller operation, the power control register (pcon) must be set to 0000b. 5. when the system clock control register, scmod, is set to 1001b, main syste m clock oscillation stops and the subsystem clock is used. 6. currents in the following circuits are not included; on-chip pull-up resistors, output port drive currents, internal lcd voltage dividing resistors, comparator.
product specification s3c7 254 4? 78 table 32 . main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in x out c1 c2 oscillation frequency (1) ? 0.4 ? 4.5 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator c1 c2 x in x out oscillation frequency (1) ? 0.4 4.19 4.5 mhz stabilization time (2) v dd = 4.5 v to 6.0 v ? ? 10 ms v dd = 2.7 v to 4.5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 4.5 mhz x in input high and low level width (t xh , t xl ) ? 111 ? 1250 ns rc oscillator r x in x out frequency v dd = 5 v 0.4 ? 2 mhz v dd = 3 v 0.4 ? 1 notes: 1. oscillation frequency and x in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval time required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
s3c7254 product specification 4? 79 table 33 . subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.7 v to 6.0 v) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in xt out c1 c2 oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 6.0 v ? 1.0 2 s v dd = 2.7 v to 4.5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs. recommended oscillator constants main system clock: ceramic resonator (ta = ?40 c ? 85 c) manufacturer product name load cap (pf) oscillator voltage range (v) remarks c1 c2 min max tdk fcr4.19mc5 ? ? 2.7 6.0 on-chip capacitor: 30 pf 20%, leaded type fcr4.19m5 33 33 2.7 6.0 leaded type ccr4.19mc3 ? ? 2.7 6.0 on-chip capacitor: 30 pf 20%, leaded type ccr1000k2 100 100 2.7 6.0 smd type
product specification s3c7 254 4? 80 table 34 . input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 35 . comparator electrical characteristics (t a = ? 40 c to + 85 c, v dd = 4.0 v to 6.0 v) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref 0 v dd input voltage accuracy v cin ? 150 mv input leakage current i cin, i ref - 3 3 a
s3c7254 product specification 4? 81 table 36 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 4.5 v to 6.0 v 0.95 ? 64 s v dd = 2.7 v to 4.5 v 3.8 64 with subsystem clock (fxt) 114 122 125 tcl0 input frequency f ti0 , f ti1 v dd = 4.5 v to 6.0 v 0 ? 1 mhz v dd = 2.7 v to 4.5v 275 khz tcl0 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 4.5 v to 6.0 v 0.48 ? ? s v dd = 2.7 v to 4.5 v 1.8 sck cycle time t kcy v dd = 4.5 v to 6.0 v external sck source 800 ? ? ns internal sck source 950 v dd = 2.7 v to 4.5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 4.5 v to 6.0 v external sck source 400 ? ? ns internal sck source t kcy /2 ? 50 v dd = 2.7 v to 4.5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to sck high t sik external sck source 100 ? ? ns internal sck source 150 si hold time to sck high t ksi external sck source 400 ? ? ns internal sck source 400 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
product specification s3c7 254 4? 82 table 36 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.7 v to 6.0 v) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 4.5 v to 6.0 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.7 v to 4.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 (see note) ? ? s int1, int2, int4, k0?k3 10 reset input low width t rsl input 10 ? ? s note: minimum value for int0 is based on a clock of 2t cy or 128 / fx as assigned by the imod0 register setting. cpu clock = 1/n x oscillator frequency (n = 4, 8, 64) 1 2 3 4 5 6 7 supply voltage (v) 250 khz 500 khz 750 khz 1.00 mhz 1.0475 mhz 8 khz cpu clock figure 48 . standard operating voltage range
s3c7254 product specification 4? 83 table 37 . ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 6.0 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 a release signal set time t srel ? 0 ? ? s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
product specification s3c7 254 4? 84 timing waveforms t srel t wait v dd reset execution of stop instruction v dddr data retention mode stop mode internal reset operation idle mode operating mode figure 49 . stop mode release timing when initiated by reset reset v dd execution of stop instruction v dddr data retention mode stop mode t wait t srel idle mode normal operating mode power-down mode terminating signal (interrupt request) figure 50 . stop mode release timing when initiated by interrupt request
s3c7254 product specification 4? 85 measurement points 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd figure 51 . a.c. timing measurement points (except for x in and xt in ) xin t xl t xh 1 / fx v dd 0.4 v figure 52 . clock timing measurement at x in xtin t xtl t xth 1 / fxt v dd ? 0.5 v 0.4 v figure 53 . clock timing measurement at xt in
product specification s3c7 254 4? 86 tcl0 t til t tih 1 / f ti 0.8 v dd 0.2 v dd figure 54 . tcl timing reset t rsl 0.2 v dd figure 55 . input timing for reset reset signal int0, 1, 2, 4 k0 to k3 t intl t inth 0.8 v dd 0.2 v dd figure 56 . input timing for external interrupts and quasi-interrupts
s3c7254 product specification 4? 87 sck t kl t kh t kcy 0.8 v dd input data output data 0.2 v dd 0.8 v dd 0.2 v dd si so t sik t ksi t kso figure 57 . serial data transfer timing
product specification s3c7 254 4? 88 characteristic curves note the characteristic values shown in the following graphs are based on actual test measurements. they do not, however, represent guaranteed operating values. i ol (ma) 1.2 2.4 3.6 4.8 v ol (v) 0 0.6 1.8 3.0 4.2 50 40 30 20 10 5 15 25 35 45 6.0 5.4 v dd = 6.0 v v dd = 4.5 v figure 58 . i ol vs. v ol (ports 0,2,3,4)
s3c7254 product specification 4? 89 i ol (ma) 0.9 1.8 2.7 3.6 v ol (v) 0 0.45 1.35 2.25 3.15 14.67 11.74 8.80 5.87 2.93 1.467 4.40 7.34 10.27 13.20 4.5 4.05 v dd = 6.0 v v dd = 4.5 v figure 59 . i ol vs. v ol (port 5) v oh (v) i oh (ma) 1.2 2.4 3.6 4.8 0 0.6 1.8 3.0 4.2 ? 22 ? 16 ? 12 ? 8 ? 4 ? 2 ? 6 ? 10 ? 14 ? 18 6.0 5.4 ? 20 v dd = 6.0 v v dd = 4.5 v figure 60 . i oh vs. v oh (ports 0,2,3,4)
product specification s3c7 254 4? 90 v dd = 4.5 v i oh (ma) 1.2 2.4 3.6 4.8 v oh (v) 0 0.6 1.8 3.0 4.2 ? 20 ? 16 ? 12 ? 8 ? 4 ? 2 ? 6 ? 10 ? 14 ? 18 6.0 5.4 ? 22 v dd = 6.0 v figure 61 . i oh vs. v oh (port 5)
s3c7254 product specification 4? 91 i dd (a) 2 4 6 8 v dd (v) 0 1 3 5 7 4000 3000 2000 1000 500 1500 2500 3500 i dd1 , fx/4 i dd1 , fx/64 i dd2 , fx/64 figure 62 . i dd vs. v dd i dd1 (a) 1 2 3 4.5 frequency (mhz) 0 0.5 1.5 2.5 3.5 3000 2000 1000 500 1500 2500 4 5.5 v, fx/ 4 5.5 v, fx/ 64 figure 63. i dd1 vs. frequency
product specification s3c7 254 4? 92 1 2 4.5 frequency (mhz) 0 0.5 3000 2000 1000 500 1500 2500 3 4 i dd1 (a) 3.5 2.5 1.5 v dd = 6 v v dd = 5 v v dd = 4 v figure 64 . i dd1 vs. frequency vs. v dd 1 2 4.5 frequency (mhz) 0 0.5 1600 800 400 200 600 1200 3 4 i dd2 (a) 3.5 2.5 1.5 1000 1400 v dd = 6 v v dd = 5 v v dd = 4 v figure 65 . i dd2 vs. frequency vs. v dd
s3c7254 product specification 4? 93 3 5 7 v d d ( v ) 0 2 3 0 0 2 0 0 1 0 0 5 0 1 5 0 i d d ( a ) 6 4 2 5 0 i d d 3 i d d 4 figure 66 . i dd3, i dd4 vs. v dd
product specification s3c7 254 4? 94 frequency (mhz) 100 150 300 resistor ( k w) 0 50 0.5 200 250 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 (v dd = 5 v) figure 68 . frequency (fx) vs. resistor

▲Up To Search▲

Price & Availability of KS57C2504

	To Download KS57C2504 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .